A wiring within a semiconductor device such as an LSI is formed by burying a wiring material within a recess, which is formed on an insulating layer on a substrate such as a semiconductor wafer, by using a plating technique. Currently, the most widely used wiring material is Cu. A Cu wiring layer is formed by forming, within the recess, a barrier layer for suppressing diffusion of Cu, forming a seed layer on the barrier layer by electroless Cu plating and forming a wiring layer by electrolytic plating (see, for example, Patent Document 1).
However, a void may be formed in the Cu wiring layer which is formed by the aforementioned method. Further, recently, as the wiring layer is getting ever more miniaturized, a volume occupied by the barrier layer becomes non-negligible. That is, if a ratio of the volume of the barrier layer having high electric resistance with respect to the total volume prepared for forming the wiring layer increases, it is difficult to obtain a sufficiently low resistance value. Furthermore, the number of processes required to form the Cu wiring layer is too many, so that a manufacturing cost of the semiconductor device is increased.
As one approach to solve the aforementioned problem, it is being considered to use a Ni-based metal as the wiring material instead of Cu. Since the Ni-based metal is not diffused into a silicon compound which is used for forming the insulating layer, a barrier layer need not be formed separately from the wiring layer. Thus, by using the Ni-based metal wiring layer, the volume of the wiring layer can be increased, and, depending on conditions, electric resistance as low as or even lower than the electric resistance of the Cu wiring layer can be achieved. Furthermore, in case of using the Ni-based metal, a relatively high precipitation rate and a relatively high plating quality are obtained by the electroless plating method. Besides, by using the Ni-based metal, processes of forming the barrier layer and the seed layer can be omitted, so that the manufacturing cost of the semiconductor device can be reduced.
When performing the electroless plating of the Ni-based metal, if a catalyst layer serving as a catalyst of a reductive precipitation reaction is formed on an outer surface of the substrate as well as within the recess, a plating layer may be formed even on the outer surface of the substrate. This extra plating layer needs to be removed by chemical mechanical polishing (CMP). In order to cut the manufacturing cost of the semiconductor device, this CMP processing time needs to be reduced.
Patent Document 1: Japanese Patent Laid-open Publication No. 2010-185113